China's CXMT Enters Mass Production With Advanced 12nm-Class DRAM Technology
The Chinese chipmaker has started manufacturing memory using its fifth-generation process, which employs quadruple-patterning to achieve a 50% boost in die capacity.
CXMT, China's leading DRAM manufacturer, has transitioned to mass production of its fifth-generation DRAM process technology, marking a significant step forward for the country's semiconductor capabilities.
The company's G5 process achieves an active-area half-pitch of 11.95nm through quadruple-patterning lithography techniques. This half-pitch measurement translates to an active-area pitch of 23.9nm, positioning the technology within the range of other advanced 10nm-class DRAM solutions, though such metrics cannot be directly mapped to conventional node designations. Additionally, CXMT's DRAM-optimized high-K metal gate process has reduced the core cell array height to 6,762nm.
To achieve greater memory density, CXMT modified its manufacturing approach and incorporated new materials that enable storage capacitors with a depth-to-width aspect ratio of approximately 45:1. While direct comparisons with rival technologies prove difficult, SK hynix has indicated that capacitor aspect ratios exceeding 100:1 will become necessary as DRAM dimensions continue to shrink below 10nm.
A 45:1 aspect ratio means the storage capacitors are 45 times deeper than their width, allowing CXMT to reduce individual memory cell footprints and pack more arrays onto each wafer while maintaining consistent yields. However, achieving such high aspect ratios introduces substantial manufacturing challenges, including complications with etching, deposition processes, mechanical stability, and ultimately maintaining acceptable production yields.
The initial mass-produced devices utilizing G5 technology are 24Gb LPDDR5X memory chips, which have already begun production. These devices deliver 50% greater capacity compared to CXMT's previous generation of comparable products and come in two distinct package configurations suited to different mobile device requirements. According to reports from China, the 24Gb LPDDR5X products are already being integrated into mainstream Chinese flagship smartphones.
Important Qualifications
Several important limitations warrant consideration. The 11.95nm specification CXMT cites refers specifically to active-area half-pitch rather than a traditional process-node classification, making the characterization of G5 as a 12nm process a substantial oversimplification.
Furthermore, the two disclosed physical dimensions alone do not establish technological equivalence with the most advanced DRAM processes from Micron, Samsung, and SK hynix. Critical factors including density, capacitor scaling, transistor performance, power consumption, and—particularly significant for commodity memory—manufacturing yields all play essential roles in determining true competitiveness. CXMT states that G5 delivers at least 50% more gross dies per wafer than its G4 predecessor, but without specific figures, this claim remains difficult to verify. The company has also withheld yield data, preventing any assessment of actual productivity gains, usable die counts, or real manufacturing expenses per bit. Nevertheless, achieving an 11.95nm-class DRAM node represents a notable accomplishment.