DapuStor's Dual-Mode J5060 Carves Out Fast Flash From QLC Capacity
The enterprise SSD maker has unveiled a firmware approach that dedicates a portion of QLC NAND to pseudo-SLC operation, achieving seven times faster random writes at the cost of 6 to 20 percent of total capacity.
Enterprise storage vendor DapuStor has introduced a dual-mode variant of its J5060 drive that partitions NAND flash into two operating regions: one running as QLC (quad-level cell) and another as pSLC (pseudo-SLC). The firmware-driven approach allocates a fixed portion of the drive's cells to operate in the faster single-bit mode, sacrificing raw capacity to gain performance on random-write operations.
In the 30.72TB configuration, the drive reserves approximately 4TB of QLC capacity and converts it into 800GB of pSLC storage—a 5:1 conversion ratio. Two additional models set aside either 400GB or 1.2TB for the fast region, representing a capacity trade-off between 6 and 20 percent. According to DapuStor, "No dedicated SLC NAND is required," since the arrangement relies on "software-defined media configuration." The company unveiled the design last month at FMS 2026, though it has not yet disclosed pricing, customer commitments, or an availability timeline.
The J5060 line spans capacities from 15.36TB to 122.88TB in the U.2 form factor and supports PCIe 4.0 x4 connectivity. The baseline 30.72TB model delivers 30,000 random-write IOPS at 16KB block size with write latency of 35 microseconds. Endurance is rated at 0.5 DWPD (Drive Writes Per Day) sustained over five years. The pSLC region achieves more than seven times the random-write performance of standard QLC, DapuStor claims, with average 4K random-write latency dropping below 8 microseconds. The fast region also offers over 25 times the program/erase cycles available in the QLC section, though region-specific DWPD and TBW metrics remain undisclosed.
DapuStor accomplishes the performance lift through three firmware modifications: die-level isolation, optimized SLC reserve allocation, and region-aware I/O scheduling. The high-performance partition targets workloads that benefit most from low-latency writes, specifically "database journals, write-ahead logs (WALs), and metadata caches." The design aims to eliminate the need for dedicated SLC drives in scenarios where their failure could disrupt operations, though a failure of the dual-mode drive itself still results in complete data loss.
Prior Art and Competing Approaches
The NVMe specification has supported this architecture since 2019, when an NVM Express presentation at FMS 2019 outlined the goal to "enable one SKU to be configured by customer for their use case." That same conference featured an example showing how some media units could operate as a small fast region while others ran at full density. A consumer product with similar mechanics, the Enmotus/Phison FuzeDrive P200, arrived via Phison firmware and a host driver; it drew criticism for excessive pricing when reviewed in 2021, and Enmotus ceased operations that same year. Modifying QLC drives to operate entirely in SLC mode is also possible, as documented in 2024, but DapuStor's approach differs by exposing the fast region as a separate block device under storage software control.
Other vendors have pursued alternative solutions. SanDisk's strategy centers on Direct Write QLC within its UltraQLC platform, which "eliminates SLC buffering by enabling power-loss safe writes on the first pass," according to SanDisk, though performance gaps persist relative to dedicated fast storage. Micron takes a different path with its XTR, a separate cache drive that pairs with its 6000-series SSD arrays. The XTR employs 176-layer TLC entirely in SLC mode and sustains up to 35 DWPD, with QD1 write latency rated at 15 microseconds.
Unanswered Questions
While the concept carries promise, real-world validation requires testing in production environments. Several specifics about DapuStor's implementation remain unclear: the pSLC region lacks detailed specifications, the command set employed by the drive is undocumented, and it is unknown whether the region split can be modified dynamically. The usability of the arrangement depends heavily on storage software that has not yet been demonstrated. Additional information about the PCIe 5.0 sibling, the R6060, would also help round out the picture. Using multi-bit flash in single-bit mode for performance or durability gains is not novel, but reconciling those benefits with the industry's push for ever-greater capacity continues to pose design challenges.